When fabricating a non-volatile memory (NVM) cell having a split gate feature in a semiconductor wafer, erasing efficiency is associated with the thickness of an inter-poly oxide interposed between a floating gate and a control gate. An etching-back process could reduce the thickness of the inter-poly oxide at a tip of the floating gate but may damage gate dielectric layers in the peripheral regions, such as transistor regions. Furthermore, a process of etching polycrystalline silicon to form the floating gate may form an undercut in the floating gate such that a portion of a poly-oxide cap hangs over the undercut.